1. Field of the Invention
The invention relates generally to IC CMOS dynamic random access memories (DRAMS), and more particularly, to a system for controlling the timing of the sense cycle in a CMOS DRAM.
2. Description of the Relation Art
Recent advances in CMOS technology have allowed memory circuit designers to realize the power reduction inherent in CMOS design while achieving high density. However, as memory cell size decreases to allow for high density, the susceptibility of alpha particle induced soft errors in the array increases. A CMOS DRAM utilizing PMOS memory cells disposed in an N well formed in a PMOS substrate significantly reduces this soft error susceptibility.
In a CMOS DRAM, digital information is stored in the form of capacitive charge in a storage cell, which can be addressed and sensed by conventional external means. The charge increment in the storage cell is sensed by means of a CMOS sensing circuit, including PMOS and NMOS cross-coupled latches, incorporated into a common integrated circuit die. The CMOS sense amp senses the differential signal voltage developed between right and left bit lines coupled to input nodes of the sense amp. This differential signal voltage is the difference between the voltage levels on a "high" bit line and a "low bit" line. The polarity of the differential signal voltage indicates the value of the stored bit. Timing of the sense operation is critical to the correct comparison of charge on the opposing bit lines. The sense cycle time, that is, the time required of the memory to address the desired bit, allow the differential voltage signal to stabilize, and to amplify the differenial signal voltage, is a significant portion of the total read access time of the memory. In the process of accessing data, speed anc accuracy are essential and competing factors. Design tradeoffs are necessary to optimize memory access speed without sacrificing accuracy.
Designs for CMOS DRAMS utilizing CMOS sense amps have been proposed in papers by Chwang et al. entitled "A 70 ns High Density CMOS DRAM," IEEE International Solid State Conference Proceedings, 22383, p. 56; Kawamoto et al. entitled "256K/1Mb DRAMS--II," 1984 IEEE International Solid States Circuits Conference Proceedings, Feb. 24, 1984, pp. 276-277; and by Kung et al. entitled "A Sub-100 ns 56K DRAM in CMOS III Technology," 1984 IEEE International Solid States Circuits Conference Proceedings. Feb. 24, 1984, pp. 278-279.
Generally, the sense cycle described in each of these references includes the following steps:
(a) the bit lines are precharged to V.sub.CC /2 where V.sub.CC is the external voltage supply level; PA1 (b) the bit is sensed by pulling the high bit line to V.sub.CC with the PMOS cross-coupled latch of the sense amp; and PA1 (c) the lines are actively restored by pulling the low bit line to ground with the NMOS cross-coupled latch.
These sense cycles having a sense amplification phase including a sense operation followed by a restore operation have several inherent disadvantages. First, the access time is increased because only the PMOS half of the CMOS sense amp is doing the sensing. Secondly, unequal capacitances in the bit line and the complementary bit line cause the signal to be lost during the sequential PMOS pull up and the NMOS pull down of the high bit line and the low bit line, respectively. For example, if the capacitance of a given bit line were substantially smaller than the capacitance of the other bit line, the given bit line would be pulled up during the PMOS pull up operation regardless of the polarity of the differential signal voltage developed between the bit lines.
A critical aspect of the sense cycle is the control of the time delay between the initiation of the charge transfer between the storage cell and the bit line and the application of source current to the sense amplifier to amplify the differential signal voltage.
The transfer of charge is characterized by the RC time constant of the storage cell and transfer gate and, thus, the increase in the magnitude of the differential signal voltage is also characterized by this constant. To avoid sense errors, it is imperative not to begin the sense amplification phase until the differential signal voltage is near its maximum value.
In many existing systems, the charge transfer trigger and sense amplifier clock signals were clocked at a fixed delay to allow the differential signal voltage to stabilize. Systems of this type cannot be optimized for speed in order to assure functionality over a wide range of fabrication process parameters and operating conditions. Such circuit designs result in slow memories as compared with the maximum speed obtainable in circuits with the best process parameters.
A further critical aspect of the sense operation is the control of the rate at which source current is applied to the sense amplifier. If this source current is increased too quickly the signal can be lost due to parasitic capacitive coupling between the source electrodes and the bit lines.
Typical systems utilize transistors, scaled to act as linear resistors wnen their gates are activated by a digital gate signal, to control the rate of increase of the sense amp source current. At best, the dynamic characteristic achieved by these systems is only a piecewise linear approximation to an optimal dynamic characteristic.
As described above, differences between the capacitance of the bit lines can cause signal loss during an independent pull up or pull down operation. In many systems, the capacitance of bit lines is substantially equal, however, during the sense cycles a selected one of the bit lines is coupled to a memory cell so that total capacitance of the selected bit line increases to C.sub.BL +C.sub.ST. The other one of the bit lines is either coupled to a dummy memory cell or remains isolated during the sense cycle so that its total capacitance is either C.sub.BL or C.sub.BL +C.sub.D. Thus, the total capacitance of the given bit line coupled to C.sub.ST is not equal to the total capacitance of the other bit line if the other bit line remains isolated during the sense cycle or if C.sub.D is not equal to C.sub.ST. Accordingly, a sense system utilizing non-simultaneous pull up and pull down cycles could cause signal loss for these types of systems.
Therefore, a system for initializing the source clock sequence to improve accuracy without degrading speed, for controlling the rate at which the source current is applied to the sense amplifier to prevent signal loss, and for simultaneously clocking the PMOS and NMOS cross-coupled latches to sense the stored bit is needed to improve the speed and accuracy of a CMOS DRAM.